`include "../../src/Add_4.v"
`timescale 1ps/1ps

module Add_4Test;
    reg[31:0] PC;
    wire[31:0] out;

    initial
    begin
        #10 PC = 32'd10;
        #10 PC = 32'D20;
        #10 $stop;
    end


    initial
    begin
        $dumpfile("test.lxt");
        $dumpvars;
    end

    Add_4 U0(PC, out);

endmodule